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w WM8788 high performance 24-bit stereo adc wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews preliminary technical data, december 2010, rev 2.2 copyright ? 2010 wolfson microelectronics plc description the WM8788 is a high performance 24-bit stereo adc designed for lcd televisions, dvd, blu-ray and set-top box applications. a stereo pair of analogue inputs is provided; external resistors are used to configure the device for line level inputs at 1vrms or for higher input signal levels. the hi-fi adcs output 16, 20 or 24-bit stereo data on the digital audio interface. adc sample rates from 8khz to 192khz are supported; master clock (mclk) ratios of 128fs up to 768fs are possible (fs = sample rate). the digital audio interface operates in master or slave modes, and supports right-justified, left-justified and i2s modes, selectable using hardware control pins. the WM8788 is powered from a single 3.3v supply rail, connected to the avdd and refvdd pins. a power on reset (por) circuit ensures correct start-up and shut-down. the device is held in reset when mclk is not present, offering a low-power standby state. the WM8788 is supplied in a 16-pin tssop package. features ? hi-fi audio adc - 106db snr (?a? weighted - -91db thd (-1dbfs output) - sample rates 8khz to 192khz ? 2 analogue audio inputs - support for line level inputs >1vrms ? digital audio interface - master or slave operation - 16, 20 or 24-bit data format - right-justified, left-justified, i2s modes ? wide range of master clock (mclk) rates - 128fs, 192fs, 256fs, 384fs, 512fs, 768fs support ? hardware configuration control ? integrated voltage reference circuits ? single 3.3v supply ? 16-pin tssop package applications ? lcd televisions ? set-top boxes (stb) ? blu-ray / dvd players and recorders block diagram inl inr reference generator bclk adcdat lrclk vmidc avdd agnd WM8788 adc l adc r aif digital filters refvdd inlfb inrfb mclk control interface master aifmode0 osr aifmode1
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 2 table of contents description ....................................................................................................... 1 features............................................................................................................. 1 applications ..................................................................................................... 1 block diagram ................................................................................................. 1 table of contents ......................................................................................... 2 pin configuration ........................................................................................... 3 ordering information .................................................................................. 3 pin description ................................................................................................ 3 absolute maximum ratings ......................................................................... 4 recommended operating conditions ..................................................... 4 thermal performance ................................................................................. 5 electrical characteristics ...................................................................... 6 terminology ............................................................................................................. 7 signal timing requirements ....................................................................... 8 system clock timing .............................................................................................. 8 audio interface timing ......................................................................................... 9 master mode ................................................................................................................... ....................... 9 slave mode .................................................................................................................... ......................... 9 device description ....................................................................................... 10 introduction .......................................................................................................... 10 input signal path .................................................................................................. 10 analogue-to-digital converter (adc) .......................................................... 12 digital audio interface ...................................................................................... 12 digital audio interface control ............................................................................................... .. 13 master and slave mode operation ............................................................................................. 1 4 audio data formats ............................................................................................................ .............. 14 digital filter characteristics ............................................................... 16 adc filter response ............................................................................................ 16 applications information ......................................................................... 18 recommended external components ........................................................... 18 audio input paths ............................................................................................................................... 18 power supply decoupling ....................................................................................................... ...... 18 recommended external components diagram ...................................................................... 19 pcb layout considerations .............................................................................. 20 package dimensions .................................................................................... 21 important notice .......................................................................................... 22 address: ................................................................................................................... 22
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 3 pin configuration the WM8788 is supplied in a 16-pin tssop format. the pin configuration is illustrated below, showing the top-down view from above the chip. 5 6 7 89 10 11 12 refvdd avdd aifmode1 inrfb aifmode0 master osr mclk WM8788 (top view) 2 3 413 14 15 inlfb inr inl lrclk bclk 116 vmidc adcdat agnd ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8788gedt -40 c to +85 c 16-pin tssop (pb-free) msl1 260 o c WM8788gedt/r -40 c to +85 c 16-pin tssop (pb-free, tape and reel) msl1 260 o c note: reel quantity = 2,000 pin description pin no name type description 1 vmidc analogue output midrail voltage decoupling capacitor 2 inl analogue input left channel analogue input 3 inlfb analogue output left channel feedback connection 4 inr analogue input right channel analogue input 5 inrfb analogue output right channel feedback connection 6 refvdd supply adc reference positive supply 7 avdd supply analogue positive supply 8 aifmode1 digital tri-state input audio interface configuration pin 1 9 aifmode0 digital tri-state input audio interface configuration pin 0 10 master digital tri-state input audio interface master / slave select 11 osr digital tri-state input adc oversample rate select 12 mclk digital input master clock 13 lrclk digital input / output audio interface left / right clock 14 bclk digital input / output audio interface bit clock 15 adcdat digital output adc digital audio data 16 agnd supply ground
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 4 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltage (avdd, refvdd) -0.3v 4.5v voltage range digital inputs -0.7v avdd +0.7v voltage range analogue inputs -0.7v avdd +0.7v operating temperature range, t a -40oc +85oc junction temperature, t jmax -40oc +150oc storage temperature after soldering -65oc +150oc recommended operating conditions parameter symbol min typ max unit analogue and digital i/o supplies range avdd, refvdd 2.97 3.3 3.6 v ground gnd 0 v note: 1. the avdd and refvdd pins must both be connected to the same external supply voltage.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 5 thermal performance thermal analysis should be performed in the intended application to prevent the WM8788 from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd pin through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air as illustrated below in figure 1: - package top to air (radiation). - package bottom to pcb (radiation). - package pins to pcb (conduction). figure 1 heat transfer paths the temperature rise t r is given by t r = p d * ? ja - p d is the power dissipated in the device. - ? ja is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ? ja is determined with reference to jedec standard jesd51-9. the junction temperature t j is given by t j = t a +t r , where t a is the ambient temperature. parameter symbol min typ max unit operating temperature range t a -40 85 c operating junction temperature t j -40 125 c thermal resistance ? ja 95 c/w note: 1. junction temperature is a function of ambient temperature and of the device operating conditions. the ambient temperature limits and junction temperature limits must both be observed.
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 6 electrical characteristics test conditions avdd = refvdd = 3.3v, agnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, mclk = 256fs unless otherwise stated. implemented recommended calibration start-up sequence as detailed in calibrated start-up section. parameter symbol test conditions min typ max unit analogue inputs (inl, inr) maximum input signal level r in = r fb = 2k avdd/3.3 vrms input capacitance 20 pf adc input path performance (analogue input to adc) signal to noise ratio snr a-weighted, fs = 48khz 106 db unweighted, fs = 48khz 103 a-weighted, fs = 96khz 106 unweighted, fs = 96khz 103 total harmonic distortion thd -1dbfs input, master mode -91 db -1dbfs input, slave mode -88 dynamic range -60dbfs input 106 db channel separation 20hz to 20khz 100 db channel level matching 0.1 db channel phase deviation 0.1 degree power supply rejection ratio (with respect to avdd) psrr 1khz 100mv pk-pk applied to avdd 50 db digital inputs / outputs input high level 0.7 x avdd v input low level 0.3 x avdd v output high level i ol = 1ma 0.9 x avdd v output low level i oh = -1ma 0.1 x avdd v input capacitance 5 pf input leakage -1 1 a clocking mclk frequency 2.048 36.864 mhz analogue reference levels midrail reference voltage vmid -4% avdd/2 +4% v vmid resistance to ground r vmid 35 k current consumption avdd current consumption i avdd quiescent fs = 48khz, mclk = 256fs 84 ma quiescent fs = 96khz, mclk = 256fs 88 quiescent no clocks applied 1
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 7 terminology 1. signal-to-noise ratio (db) ? snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20hz to 20khz. this ratio is also called idle channel noise. (no auto-zero or mute function is employed). 2. total harmonic distortion (db) ? thd is the difference in level between a 1khz reference sine wave output signal and the first seven harmonics of the output signal. the amplitude of the fundamental frequency of the output signal is compared to the rms value of the next seven harmonics and expressed as a ratio. 3. total harmonic distortion plus noise (db) ? thd+n is the difference in level between a 1khz reference sine wave output signal and all noise and distortion products in the audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms value of all other noise and distortion products and expressed as a ratio. 4. channel separation (l/r) (db) ? is a measure of the coupling between left and right channels. a full scale signal is applied to the left channel only, and the right channel amplitude is measured. next, a full scale signal is applied to the right channel only, and the left channel amplitude is measured. the worst case channel separation is quoted; this is the difference in level between the full-scale output and the cross-channel output signal level, expressed as a ratio. 5. power supply rejection ratio (db) ? psrr is a measure of ripple attenuation between a power supply rail and a signal output path. with the signal path idle, a small sine wave ripple is applied to power supply rail. the amplitude of the supply ripple is compared to the amplitude of the output signal generated and is expressed as a ratio. 6. all performance measurements are carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out-of-band noise; although it is not audible, it may affect dynamic specification values.
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 8 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 2 master clock timing test conditions avdd = refvdd = 3.3v, agnd = 0v, t a = +25 o c. parameter symbol conditions min typ max unit master clock timing mclk frequency 1 / t mclky 2.048 36.864 mhz mclk duty cycle (= t mclkh : t mclkl ) 60:40 40:60
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 9 audio interface timing master mode bclk (output) lrclk (output) adcdat (output) t dda t dl figure 3 audio interface timing - master mode test conditions avdd = refvdd = 3.3v, agnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit audio interface timing - master mode lrclk propagation delay from bclk falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns slave mode figure 4 audio interface timing - slave mode test conditions avdd = refvdd = 3.3v, agnd = 0v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol min typ max unit audio interface timing - slave mode bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set-up time to bclk rising edge t lrsu 20 ns lrclk hold time from bclk rising edge t lrh 20 ns adcdat propagation delay from bclk falling edge t dd 20 ns
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 10 device description introduction the WM8788 is a high-performance 24-bit stereo adc designed for lcd televisions, dvd, blu-ray and set-top box applications. it is packaged in a 16-pin tssop. the device comprises two analogue input channels. external resistors are used to configure the device for line level inputs at 1vrms or for higher input signal levels. the stereo hi-fi adcs operate at sample rates from 8khz to 192khz. a high pass filter is provided in the adc path for removing dc offsets and suppressing low frequency noise. the digital audio interface can operate in master or slave mode and supports the adc output in right-justified, left-justified or i2s format. the data word size is selectable between 16, 20 or 24 bits. the device configuration is selected using hardware control inputs. the digital control inputs use tri- state logic in order to support many different configuration selections. the WM8788 incorporates an internal voltage reference and ldo regulator for power-efficient operation from a single power supply. external clocking is required via the mclk pin. a power on reset (por) circuit ensures correct start-up and shut-down. the WM8788 is held in reset when mclk is not present, offering a low-power standby state. calibrated start-up the WM8788 chip has a phase calibration circuit that is active in slave mode. this circuit detects incoming clock phase relationship and configures the device automatically to ensure best performance of the device. phase calibration starts as soon as the device comes out of reset, and takes 64 bclk periods from power on reset to complete. note that once the clock signals are calibrated and in phase, no further calibration will take place until the device next comes out of reset. for the phase calibration to work effectively, the calibration must take place when the mclk and the bclk signals are stable with a fixed phase relationship and running at the frequency which the device will eventually operate. there are three different sequences that allow the system designer to ensure that this can happen: 1. ensure that mclk and bclk have a fixed phase relationship before lrclk is applied 2. after power-up, pause lrclk for a minimum of 1 period 3. after power-up, stop mclk for a minimum of 20 periods. then re-start mclk in a fixed phase and frequency relationship to bclk in option (1), the device will be held in reset if no lrclk is applied. mclk and blck must be in a fixed and final operation phase relationship and frequency before lrclk is applied. options (2) and (3) both digitally reset the device, and can be used if the clock relationship changes during operation to allow re-calibration to the new relationship. if sample rate is changed, it is recommended that either option 2 or option 3 above is carried out once the sample rate change is complete. note that phase calibration only takes place in slave mode. in master mode, the phase calibration circuit is not required and is disabled.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 11 input signal path the WM8788 supports two analogue input channels. the recommended input circuit configuration for the left input channel is illustrated in figure 5. this is suitable for single-ended connection to line level input signals. figure 5 input signal path configuration the right input channel is identical to the left input channel. the feedback input pins inlfb and inrfb are used to provide an adjustable gain in t he input circuit, enabling input signals greater than 1vrms to be supported. the maximum analogue input signal level varies with avdd and with the input circuit configuration, as described in the following equation: see ?applications information? for details of the recommended external components.
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 12 analogue-to-digital converter (adc) the WM8788 uses two 24-bit sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. all common sample rates from 8khz to 192khz are supported; these are selected as described in the ?digital audio interface? section. digital filters are also incorporated on the adc output signal path to remove dc offsets and other unwanted noise. the cut-off frequency of the adc high-pass filter varies with the adc sample rate (fs), but is typically 4hz when fs = 48khz. filter response plots for the adc high-pass filter are shown in ?digital filter characteristics?. digital audio interface the digital audio interface is used for outputting adc data from the WM8788. it uses three pins: ? adcdat - adc data output ? lrclk - left / right data alignment clock ? bclk - bit clock, for synchronisation the configuration of the digital audio interface is determined by the logic levels on the following hardware control pins: ? master - master / slave mode select ? osr - adc oversample rate select ? aifmode0 - audio interface configuration select 0 ? aifmode1 - audio interface configuration select 1 the digital audio interface supports right-justified, left-justified and i2s formats. the data word size can be 16, 20 or 24-bits. audio sample rates (fs) from 8khz to 192khz are supported. a master clock (mclk) is required at one of the typical clocking ratios 128fs, 192fs, 256fs, 384fs, 512fs and 768fs. the WM8788 can operate in master mode or in slave mode. in master mode, lrclk and bclk are generated by the WM8788. in slave mode, lrclk and bclk are inputs to the WM8788. the digital audio interface is configured using the hardware control pins master, osr, aifmode0 and aifmode1. note that these pins are tri-state digital inputs. the logic 1 and logic 0 voltage levels are referenced to the avdd power domain. a logic ?z? is a high-impedance condition which is selected when the pin is floating and not connected. a description of the hardware control pins is provided in the ?digital audio interface control? section below. the digital audio interface protocols are described in the ?master and slave mode operation? and ?audio data formats? sections.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 13 digital audio interface control the digital audio interface protocol is selected using the control pins aifmode0 and aifmode1, as described in table 1. aifmode1 aifmode0 format 0 0 16-bit right-justified 0 1 20-bit right-justified 0 z 24-bit right-justified 1 0 16-bit left-justified 1 1 20-bit left-justified 1 z 24-bit left-justified z 0 16-bit i2s z 1 20-bit i2s z z 24-bit i2s table 1 digital audio interface mode select for slave mode, set master = 0 and set osr according to the applicable sample rate. master osr sample rate 0 0 8, 16, 32, 44.1, 48khz 0 1 88.2, 96khz 0 z 176.4, 192khz table 2 slave mode configuration in slave mode, the mclk and lrclk inputs must conform to a valid clocking ratio, as noted below. the lrclk frequency is the same as the sample rate, fs. mclk frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs can be supported, depending on the sample rate. the bclk signal is an input to the WM8788 in slave mode. a range of bclk frequencies can be supported, provided there are sufficient bclk cycles for the selected data word length. the bclk frequency must not be higher than the mclk frequency, and must not be higher than 12.288mhz. sample rate mclk frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 8khz n/a n/a 2.048 3.072 4.096 6.144 16khz n/a n/a 4.096 6.144 8.192 12.288 32khz n/a n/a 8.192 12.288 16.384 24.576 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 48khz n/a n/a 12.288 18.432 24.576 36.864 88.2khz 11.2896 16.9344 22.5792 33.8688 n/a n/a 96khz 12.288 18.432 24.576 36.864 n/a n/a 176.4khz 22.5792 33.8688 n/a n/a n/a n/a 192khz 24.576 36.864 n/a n/a n/a n/a table 3 mclk frequency in slave mode
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 14 for master mode, set master and osr according to the applicable sample rate and clocking ratio. master osr clocking ratio sample rate 1 0 384fs 8, 16, 32, 44.1, 48khz 1 1 384fs 88.2, 96khz z 0 256fs 8, 16, 32, 44.1, 48khz z 1 256fs 88.2, 96khz table 4 master mode configuration in master mode, the sample rate (fs) is determined by the mclk frequency and by the selected clocking ratio. the lrclk frequency is the same as the sample rate, and is output by the WM8788 in master mode. the bclk signal is output by the WM8788 in master mode. the bclk frequency is lrclk x 64. master and slave mode operation the digital audio interface can be configured as a master or a slave interface, depending on the state of the master control pin described earlier. the two modes are illustrated in figure 6 and figure 7. figure 6 master mode figure 7 slave mode in master mode, lrclk and bclk are configured as outputs, and the WM8788 controls the timing of the data transfer on the adcdat pin. in master mode, the lrclk frequency is determined automatically according to the mclk frequency and the selected clocking ratio. the bclk frequency is lrclk x 64. in slave mode, lrclk and bclk are configured as inputs, and the data timing is controlled by an external master. audio data formats three audio data formats are supported by the digital audio interface: ? right-justified ? left-justified ? i 2 s all of these modes are msb first, and are illustrated below. refer to the ?signal timing requirements? section for timing information. in right justified mode, the lsb is available on the last rising edge of bclk before a lrclk transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 15 figure 8 right justified audio interface (assuming n-bit word length) in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 9 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 10 i 2 s justified audio interface (assuming n-bit word length)
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 16 digital filter characteristics parameter test conditions min typ max unit passband +/- 0.1db 0 0.454 fs -6db 0.5fs passband ripple +/- 0.1 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db group delay 16.5 / fs s terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region adc filter response magnitude( db) 0 17.64k 35.28k 52.92k 70.56k 88.2k 105.8k 123.5k 141.1k 158.8k 176.4k -200 -180 -160 -140 -120 -100 -80.01 -60.01 -40.01 -20 -2.2m 20 db figure 11 adc frequency response up to 4 x fs (sample rate, fs = 48khz)
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 17 magnitude( db) 0 2k 3.999k 5.999k 7.999k 9.998k 12k 14k 16k 18k 20k -31.35m -25.4m -19.46m -13.51m -7.561m -1.614m 4.333m 10.28m 16.23m 22.18m 28.12m 34.07m db figure 12 adc pass band frequency response up to fs/2 (sample rate, fs = 48khz) 0 -5 -10 -15 -20 -25 -30 20 15 10 5 0 figure 13 adc high pass filter frequency response (sample rate, fs = 48khz)
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 18 applications information recommended external components audio input paths the WM8788 provides 2 analogue audio inputs. the maximum analogue input signal level varies with avdd and with the input circuit configuration, as described in the following equation: it is recommended that the resistors r in and r fb should not exceed 10k . for 1vrms (0dbv) maximum input signal level when avdd = 3.3v, the recommended input components are r in = 2k , r fb = 2k . for 2vrms (6dbv) maximum input signal level when avdd = 3.3v, the recommended input components are r in = 2k , r fb = 1k . the input pins inl and inr are referenced to the internal dc reference, vmid. a dc blocking capacitor is required for each input. the choice of capacitor is determined by the filter that is formed between that capacitor and the input resistor, r in . the circuit is illustrated in figure 14. figure 14 input signal path external components it is recommended that an input capacitor is selected such that the fc cut-off frequency is less than 20hz. it is recommended that a 4.7 f capacitance is used for all WM8788 input connections. tantalum electrolytic capacitors are particularly suitable as they offer high stability in a small package size. see wolfson applications note wan_0176 for further guidance on the choice of capacitor types. power supply decoupling electrical coupling exists particularly in digital logic systems where switching in one sub-system causes fluctuations on the power supply. this effect occurs because the inductance of the power supply acts in opposition to the changes in current flow that are caused by the logic switching. the resultant variations (or ?spikes?) in the power supply voltage can cause malfunctions and unintentional behavior in other components. a decoupling (or ?bypass?) capacitor can be used as an energy storage component which will provide power to the decoupled circuit for the duration of these power supply variations, protecting it from malfunctions that could otherwise arise.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 19 coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the load current or by limitations of the power supply regulation method. in audio components such as the WM8788, these variations can alter the performance of the signal path, leading to degradation in signal quality. a decoupling (or ?bypass?) capacitor can be used to filter these effects, by presenting the ripple voltage with a low impedance path that does not affect the circuit to be decoupled. these coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground reference. in the case of systems comprising multiple power supply rails, decoupling should be provided on each rail. the recommended power supply decoupling capacitors for WM8788 are listed below in table 5. power supply decoupling capacitor avdd 4.7 f ceramic refvdd 4.7 f ceramic vmidc 4.7 f ceramic table 5 power supply decoupling capacitors all decoupling capacitors should be placed as close as possible to the WM8788 device. the vmidc capacitor is not, technically, a decoupling capacitor. however, it does serve a similar purpose in filtering noise on the vmid reference. the connection between gnd, the vmid decoupling capacitor and the main system ground should be made at a single point as close as possible to the gnd pin of the WM8788. due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components provide the required capacitance across the required temperature and voltage ranges in the intended application. for most application the use of ceramic capacitors with capacitor dielectric x5r is recommended. see wolfson applications note wan_0176 for further guidance on the choice of capacitor types. recommended external components diagram figure 15 provides a summary of recommended external components for WM8788. note that the actual requirements may differ according to the specific target application. figure 15 WM8788 recommended external components diagram
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 20 pcb layout considerations poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. all external components should be placed as close to the WM8788 device as possible, with current loop areas kept as small as possible.
preliminary technical data WM8788 w ptd, december 2010, rev 2.2 21 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 mo-153, variation = ab. refer to this specification for further details. dm013.b dt: 16 pin tssop (5.0 x 4.4 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 d 4.90 5.00 5.10 e 0.65 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.45 0.60 0.75 0 o ----- 8 o ref: jedec.95, mo-153 a a2 a1 c l gauge plane 0.25 8 1 d 9 16 e1 e e b seating plane -c- 0.1 c
WM8788 preliminary technical data w ptd, december 2010, rev 2.2 22 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised [ to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise [ risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise [ inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised [ alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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